Getting started · Tool reference · Architecture · 中文

Let an AI agent inspect waveforms, trace signal drivers, and navigate RTL in a
live Synopsys Verdi session, locally or over SSH.

“Add the FIFO read/write pointers, go 20 cycles before the error, and investigate why full stayed high.”

“Why did this AXI-Lite response disappear before BREADY?”

The agent reasons about the design. Verdi Bridge provides ten typed MCP tools that
return waveform values and source evidence while operating the GUI you can inspect.

Video walkthrough

Ask an agent to investigate a bug, then watch it choose signals, inspect live waveforms and navigate RTL. A 1m38s silent demo: an English prompt and original English agent replies beside synchronized Verdi capture. This is a separate English-language run, not a translation. Tool calls are selected by the agent, not a replay script.

https://github.com/user-attachments/assets/b041c1bd-4be5-4040-b281-2f15001b1e35

English video · 中文视频

How this was recorded · Installation tutorial

Quick start

git clone https://github.com/RuihongY/verdi_bridge.git
cd verdi_bridge
uv sync
uv run verdi-bridge tcl-path   # adapter to load in your Verdi session

Next, load the adapter and connect your MCP client.
You need a licensed Verdi installation; no vendor software is bundled.
Python 3.11+ runs on the client; an SSH host only needs Python 3.6+ and Verdi's Tcl 8.6.
The package is installed from this repository, not a published PyPI release.

What you can do

Workflow	Tools
Find and display signals	`browse_scope`, `add_signals`
Navigate an error window	`set_cursor`, `set_time_window`, `jump_before_error`
Inspect actual waveform values	`sample_signals`, `session_status`
Follow drivers into RTL	`trace_driver`, `read_source`, `goto_source`

Waveform queries preserve X/Z values. Time arguments carry explicit units.
The same interface works with different RTL designs; no FIFO-specific logic is
built into the bridge. See the Python and CLI examples.

Tested on real RTL

UART TX, an AXI-Lite write interface, and a round-robin arbiter were tested using
VCS and Verdi. Across 27 simulation runs, all nine baseline runs passed, all
nine injected-bug runs failed their checkers, and all nine repaired runs passed.
The seed-1 cases were inspected through real MCP calls and a live Verdi GUI.

Design	Observed fault
UART	A short frame counter entered the stop bit too early
AXI-Lite	BVALID disappeared while BREADY was low
Arbiter	The rotation mask was cleared instead of stored

Evidence and screenshots ·
Reproduce these experiments ·
Earlier FIFO cases

These are known, locally injected mutations, not upstream defects or a blinded
accuracy benchmark. Driver tracing can return an initializer rather than the fault;
source inspection and waveform reasoning remain necessary.

A separate independent-agent blind trial used three
new bugs: the fresh-context diagnostician identified all three exact statements
with 21 live MCP calls, and its proposed repairs passed 9/9 runs. Answers were
frozen before revealing mutations. This was procedural isolation on a shared
filesystem, a small trial with no RTL-only comparison.

View a real Verdi debugging session

UART waveform and source in Verdi

Project status

Experimental v0.1.1. Tested with Verdi T-2022.06-SP2-1 on Linux.
New-session startup is verified; attachment to an arbitrary existing GUI is not yet
separately validated. The bridge does not automatically compile, edit or repair RTL.

Contributing · Trust boundary ·
Validation limits · Report an issue

Inspired by the agent-to-EDA-tool workflow of
virtuoso-bridge-lite.
This is an independent implementation. MIT licensed; see third-party notices.
Not affiliated with Synopsys. Verdi is a Synopsys trademark.

Video walkthrough

Quick start

What you can do

Tested on real RTL

Project status

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