EDA_MCP: Agentic Full-Flow EDA Control Plane & Autonomous Chip Design Workspace

Transforming AI Coding Agents into Autonomous Silicon & IC Design Engineers.
EDA_MCP is a high-performance Model Context Protocol (MCP) server that connects local AI IDEs and agents (Antigravity, Cursor, Windsurf, Claude Desktop, Claude Code) directly to remote Linux EDA compute clusters executing Cadence Virtuoso and Siemens Eldo.

Through EDA_MCP, AI agents autonomously execute the complete, closed-loop IC design lifecycle—from schematic capture and PDK transistor sizing to Layout XL generation, Calibre DRC physical verification, Calibre LVS equivalence checking, Calibre xRC parasitic extraction (PEX), and post-layout analog SPICE simulation verification.

📹 Demo Video

(Video Source: doc/media/demo.mp4)

💡 Experiment & Solve Real-World IC Design Problems: Use EDA_MCP to interactively build custom integrated circuits, run physical layout verification pipelines, perform SPICE simulations, and solve silicon design challenges.
🎓 Live Demonstration: The video demonstration above showcases an AI agent interactively constructing, transistor sizing, CDL netlisting, and simulating a depletion-load inverter live inside Cadence Virtuoso and Siemens Eldo.

⚡ Full-Flow Autonomous Silicon Engineering Capabilities

[!IMPORTANT]
Verified Full-Flow Baseline (Issue #53 CheckPoint Milestone): EDA_MCP empowers AI agents to execute complete end-to-end silicon design flows autonomously. In a single continuous session, an AI agent can build a multi-stage analog/digital block, layout physical silicon, resolve design rules, verify layout-versus-schematic (LVS) match, extract 700+ parasitic R/C elements, and validate post-layout analog performance.

Here is the complete suite of silicon engineering tasks AI agents can perform through EDA_MCP:

┌───────────────────┐    ┌───────────────────┐    ┌───────────────────┐    ┌───────────────────┐    ┌───────────────────┐    ┌───────────────────┐
│ 1. SCHEMATIC &    │──► │ 2. VIRTUOSO       │──► │ 3. SIEMENS        │──► │ 4. SIEMENS        │──► │ 5. PARASITIC      │──► │ 6. ELDO POST-PEX  │
│    PDK SIZING     │    │    LAYOUT XL      │    │    CALIBRE DRC    │    │    CALIBRE LVS    │    │    EXTRACTION     │    │    ANALOG SPICE   │
│ (cmos065 schCheck)│    │ (GFS, VSR, Vias)  │    │ (100% Clean SVRF) │    │  (0 Mismatches)   │    │ (Calibre xRC PEX) │    │ (AC/DC/Tran/Power)│
└───────────────────┘    └───────────────────┘    └───────────────────┘    └───────────────────┘    └───────────────────┘    └───────────────────┘

1. 📐 Schematic Capture & PDK Sizing (Virtuoso)

• Automated Schematic Generation: Programmatically builds complex analog and digital schematics (Op-Amps, logic gates, bias networks, bandgaps) inside Cadence Virtuoso.
• Foundry PDK Device Sizing: Drives $65\text{nm}$ LP/GP transistor sizing (psvtgp, nsvtgp) with exact micron width/length parameters ($W, L$) and executes foundry CDF callbacks (DK_mosInit).
• Zero-Warning ERC Validation: Programmatically executes schCheck, strictly enforcing 0 errors and 0 warnings ((0 0)) before netlist compilation.

2. 🎨 Virtuoso Layout XL Generation & Optimization (Layout XL)

• Connectivity-Bound Application Launch: Programmatically opens Layout XL tiers (lxSetConnRef $\rightarrow$ deOpen in "Layout XL") with active schematic correspondence and cross-probing.
• Generate From Source (GFS): Automates device instantiation, Metal 1 pin retargeting, net binding (lxGenerateStart / lxSetNetPinSpecs / lxGenerateFinish), and Metal 1 drawing enclosure compliance (M1.PIN.CAD.1).
• Advanced Silicon Layout Practices: Programmatically places OpenAccess standard vias (M1__PO, M1__NW, M1__PT), snaps coordinates to the $5\text{nm}$ manufacturing grid, builds continuous dual-tap straps (LUP.D.1_LUP.D.2), and optimizes diffusion geometries.
• Automated Placement & Routing: Invokes Virtuoso Layout XL analog placement (nclAnalogQuickPlaceLikeSchemCB) and Virtuoso Space-Based Routing (VSR) engines.

3. 🔍 Physical Verification (Siemens Calibre DRC)

• Headless GDSII Stream-Out: Programmatically streams layout GDSII files (strmout) using official PDK layer maps (cmos065.layermap) and case preservation.
• Hierarchical SVRF Control: Authors custom SVRF decks (drc.svrf), handles leaf-cell density rules (ALL_DENSITY_CHECK), and executes calibre -drc -hier.
• Real-Time Virtuoso Viewport Debugging: Converts nanometer database coordinates to user microns, pans the Virtuoso GUI canvas (hiPan), highlights error markers (dbCreateMarker), and applies surgical layout fixes to achieve 100% clean DRC reports.

4. ⚖️ Layout-Versus-Schematic (Siemens Calibre LVS)

• Automated Netlist Extraction: Programmatically extracts structural SPICE netlists from schematic databases and physical GDSII geometry.
• 100% Equivalence Verification: Executes Siemens Calibre LVS, verifying 0 mismatches, 0 short circuits, 0 open circuits, and 0 device parameter discrepancies between schematic and layout.

5. ⚡ Parasitic Extraction (Siemens Calibre xRC / PEX)

• Full Transistor & Interconnect Extraction: Executes Siemens Calibre xRC (calibre -xrc -pdb -rcc) to calculate parasitic resistance ($R$) and capacitance ($C$) networks across all metal and via layers.
• Post-Layout Extracted SPICE Decks: Generates detailed .pex.spi subcircuits capturing hundreds of parasitic components (e.g. 793 total parasitics: 347 R, 446 C in a $65\text{nm}$ Op-Amp layout).

6. 📊 Siemens Eldo Analog SPICE Simulation (Pre-Layout vs Post-Layout PEX)

• Interactive & Batch SPICE Engine: Manages continuous interactive SPICE REPL streams (eldo -inter), truncates logs, and parses .extract measurement reports.
• Post-Layout Parasitic Verification: Simulates extracted PEX decks (.include "<cell>.pex.spi") alongside pre-layout schematics to measure real-world silicon degradation:
  • Small-Signal AC Analysis: DC open-loop gain ($A_{v0}$), $-3\text{dB}$ bandwidth ($f_{-3\text{dB}}$), Gain Bandwidth Product ($GBW$), Phase Margin ($PM$).
  • DC Transfer Sweeps: Input offset voltage ($V_{\text{os}}$), output swing limits ($V_{\text{OH}}, V_{\text{OL}}$).
  • Transient Step Response: Large/small signal step response, positive/negative slew rates ($SR_+, SR_-$), settling time.
  • Power & Noise: Static/dynamic power consumption, input-referred noise spectral density.
  • Multi-Corner PVT Sweeps: Automated simulation across process corners (typNtypP, minNminP, maxNmaxP, maxNminP, minNmaxP).

7. 🗂️ Git-Backed Workspace Synchronizer (WorkBoard)

• Local-Remote Workspace Synchronization: Tracks remote Linux EDA cluster files in local Git repositories (./workboard/<name>/).
• Safe Delta Diffing: Computes unified line-by-line diffs before committing edits back to remote servers, preventing file corruption and enabling full rollback history.

8. 🤖 Autonomous Bug Reporting & Inter-Agent Peer Review (agent-landline)

• Self-Healing Meta-Harness: Submits detailed GitHub issue reports (report_issue) with auto-attached execution logs, agent headers, and session IDs.
• Inter-Agent Landline Communication: Enables Coder and Designer agents to communicate, peer-review code, and verify edge cases across active sessions using agent-landline.

🧠 Multi-Agent Collaboration, Knowledge Base & Mind Map

For developers new to agentic workflows, EDA_MCP orchestrates specialized AI agents working concurrently across distinct roles (e.g. a Coder Agent maintaining the MCP backend vs a Designer Agent driving Cadence Virtuoso & Siemens Eldo).

Agents consult a structured Knowledge Base (domain context specifications) and coordinate through a shared Mind Map / Active Memory Layer (agent-landline IPC, WorkBoard manifests, and session checkpoints):

graph TB
    subgraph KnowledgeBase["📚 KNOWLEDGE BASE & DUAL-TRACK SPECIFICATIONS"]
        subgraph DesignerSpec["Designer Domain Specs (context/designer/)"]
            D1["• PDK Rules: cmos065 65nm LP/GP<br/>• Device Sizing: psvtgp / nsvtgp<br/>• Layout XL & GFS Directives<br/>• Calibre DRC/LVS SVRF Specs"]
        end
        subgraph CoderSpec["Coder Domain Specs (context/coder/)"]
            C1["• FastMCP Server & Transport Specs<br/>• Git Branching & PR Workflows<br/>• Landline Collaboration Directives<br/>• MCP Process Reload & Signals"]
        end
    end

    subgraph Memory["🧠 MIND MAP & ACTIVE WORKSPACE MEMORY"]
        M1["• Inter-Agent Landline IPC (agent-landline)<br/>• WorkBoard State Registry (.workboard.json)<br/>• Issue Tracker & Session Checkpoints"]
    end

    subgraph Agents["🤖 AUTONOMOUS AI AGENTS"]
        subgraph CoderAgent["Coder / Maintainer Agent"]
            CA["<b>Coder Agent</b><br/><i>(Codebase & Server Engineer)</i>"]
            CA_Do["• Modifies Python FastMCP Server<br/>• Maintains SSH/SCP Transports<br/>• Runs Unit Test Suites<br/>• Opens GitHub PRs"]
        end

        subgraph DesignerAgent["Chip Designer Agent"]
            DA["<b>Designer Agent</b><br/><i>(Silicon IC Design Engineer)</i>"]
            DA_Do["• Builds Schematics & Sizes PDK W/L<br/>• Drives Cadence Virtuoso Layout XL<br/>• Fixes Calibre DRC & Verifies LVS<br/>• Runs Eldo Pre-/Post-PEX SPICE Sims"]
        end
    end

    subgraph Execution["⚡ REMOTE EDA CLUSTER ENGINES"]
        E_VIRT["Cadence Virtuoso GUI / FIFO Pipe"]
        E_ELDO["Siemens Eldo SPICE Simulator"]
        E_CAL["Siemens Calibre (DRC / LVS / PEX)"]
        E_PY["EDA_MCP FastMCP Server Core"]
    end

    %% Relations
    DesignerSpec ==>|PDK & Tool Guidance| DA
    CoderSpec ==>|Architecture & Git Guidance| CA

    CA <==>|Peer Review & Bug Reporting| Memory
    DA <==>|Session Checkpoints & Feedback| Memory

    CA -->|Maintains Codebase| E_PY
    DA -->|Drives Schematic & Layout| E_VIRT
    DA -->|Runs Interactive SPICE| E_ELDO
    DA -->|Executes Physical Verification| E_CAL

🤖 Agent Directives & Dual-Track Context Routing

EDA_MCP includes the eda-mcp-context-router directive, enabling AI agents to autonomously inspect domain specifications before execution:

flowchart TD
    Intent["<b>AI AGENT</b><br/><i>Task Intent Classification</i>"]
    
    Intent -->|Circuit Design / Layout / Sim| Track1["<b>TRACK 1: CIRCUIT DESIGN & SIM</b><br/><i>Inspect: context/designer/README.md</i>"]
    Intent -->|Codebase Dev / Bug Fixing / PRs| Track2["<b>TRACK 2: CODEBASE & MAINTENANCE</b><br/><i>Inspect: context/coder/README.md</i>"]

    subgraph Track1Spec["Track 1 Directives"]
        T1_1["• PDK: cmos065 (65nm LP/GP)"]
        T1_2["• Devices: psvtgp (PMOS), nsvtgp (NMOS)"]
        T1_3["• CDF Units: Width/Length as Micron strings"]
        T1_4["• Layout XL: lxSetConnRef & GFS Rules"]
        T1_5["• Calibre DRC: strmout layer map & SVRF"]
        T1_6["• Calibre LVS & xRC PEX Extraction"]
        T1_7["• Validation: schCheck (0 0) required"]
    end

    subgraph Track2Spec["Track 2 Directives"]
        T2_1["• Branching: agent/issue-id-desc"]
        T2_2["• Custom Git Agent Author metadata"]
        T2_3["• Automated PR header generation"]
        T2_4["• STRICT NO-AUTOMERGE policy"]
        T2_5["• Test suite validation"]
        T2_6["• Inter-Agent Landline Peer Review"]
    end

    Track1 --- Track1Spec
    Track2 --- Track2Spec

• 📘 Designer Context Guide: context/designer/README.md
  • 📐 Schematic Flow
  • 🎨 Layout XL Flow
  • 🔍 Calibre DRC Flow
  • ⚡ Eldo Simulation Guide
• 📙 Coder Context Guide: context/coder/README.md

💡 Why EDA_MCP? Thoughtful Workspace Technology

Modern Integrated Circuit (IC) design demands high-performance Linux compute clusters hosting multi-gigabyte EDA tool suites (Cadence Virtuoso, Siemens Eldo) and proprietary PDKs (e.g. cmos065). However, AI developer tools and LLM agents operate locally inside modern IDEs.

EDA_MCP bridges this divide with an ultra-lightweight, resilient architecture built on 6 foundational pillars:

1. ⚡ Sub-10ms SSH Multiplexing Engine: Eliminates SSH handshake overhead by using persistent OpenSSH ControlMaster unix domain sockets and streaming file transport (ssh_client.py & scp_client.py).
2. 🗂️ Git-Backed WorkBoard Workspace (workboard): Local-remote workspace synchronizer that mirrors, tracks, versions, and computes unified line-by-line diffs for remote EDA files locally before pushing edits back to the cluster (workboard_client.py).
3. 🎨 Window-First Live GUI & Virtuoso IPC (virtuoso): Drives Cadence Virtuoso schematic, Layout XL, and SKILL execution live inside an open GUI window or non-graphical session via named FIFO pipes (MCP.command) and IPC socket handlers (virtuoso_client.py).
4. ⚡ Interactive Eldo SPICE Engine (eldo): Manages continuous interactive SPICE REPL streams (eldo -inter), truncates logs, parses .extract measurement reports, and runs batch simulation decks (eldo_client.py).
5. 📊 PyQtGraph SPICE Waveform Oscilloscope: Features eldo_plotter.py, a multi-pane interactive waveform visualizer supporting .raw and .spi3 SPICE transient analysis files with linked time axes, dynamic signal legends, and crosshair readouts.
6. 🤖 Autonomous Dual-Track Context Router (eda-mcp-context-router): Equips AI agents with strict domain specs (context/designer for circuit design, Layout XL, Calibre DRC & PDK rules, context/coder for server maintenance & GitHub PR workflows), plus an agent-to-agent bug reporting pipeline (report_issue).

🏛️ System Architecture

┌─────────────────────────────────────────────────────────────────────────────────────────┐
│                              LOCAL SYSTEM (Developer / AI Agent)                        │
│                                                                                         │
│  ┌───────────────────────────────────────────────────────────────────────────────────┐  │
│  │                              EDA_MCP (FastMCP Server)                             │  │
│  │                                                                                   │  │
│  │   ┌───────────────┐   ┌───────────────┐   ┌───────────────┐   ┌───────────────┐   │  │
│  │   │  workboard    │   │   virtuoso    │   │     eldo      │   │remote_control │   │  │
│  │   └───────┬───────┘   └───────┬───────┘   └───────┬───────┘   └───────┬───────┘   │  │
│  └───────────┼───────────────────┼───────────────────┼───────────────────┼───────────┘  │
└──────────────┼───────────────────┼───────────────────┼───────────────────┼──────────────┘
               │                   │                   │                   │
               │        OpenSSH ControlMaster Socket (Sub-10ms Latency)    │
               ▼                   ▼                   ▼                   ▼
┌─────────────────────────────────────────────────────────────────────────────────────────┐
│                              REMOTE EDA LINUX SERVER / CLUSTER                          │
│                                                                                         │
│  ┌────────────────────┐ ┌────────────────────┐ ┌────────────────────┐ ┌──────────────┐  │
│  │  Git Workspace /   │ │  Cadence Virtuoso  │ │    Siemens Eldo    │ │ Process PDKs │  │
│  │  WorkBoard Sync    │ │  SKILL IPC FIFO    │ │   SPICE Simulator  │ │  (cmos065)   │  │
│  ├────────────────────┤ ├────────────────────┤ ├────────────────────┤ └──────────────┘  │
│  │ Calibre DRC / LVS  │ │ Virtuoso Layout XL │ │ Calibre xRC PEX    │                   │
│  └────────────────────┘ └────────────────────┘ └────────────────────┘                   │
└─────────────────────────────────────────────────────────────────────────────────────────┘

IPC Data Flow Architectures

🎨 Cadence Virtuoso Named Pipe FIFO Architecture

sequenceDiagram
    autonumber
    actor Agent as Local AI Agent
    participant MCP as FastMCP (virtuoso)
    participant SSH as SSH ControlMaster
    participant FIFO as FIFO Pipe (MCP.command)
    participant Daemon as IPC Handler (MCP_sockit.py)
    participant Virtuoso as Virtuoso CIW / GUI Window

    Agent->>MCP: virtuoso(action="assisted_run", script="...")
    MCP->>SSH: Stream SKILL command
    SSH->>FIFO: Write to MCP.command
    FIFO->>Daemon: Read SKILL payload
    Daemon->>Virtuoso: evalstring() execution
    Virtuoso-->>Daemon: Return result & status
    Daemon-->>SSH: Write output to mcp_output.txt
    SSH-->>MCP: Read mcp_output.txt sentinel
    MCP-->>Agent: Return JSON tool response

⚡ Siemens Eldo Interactive SPICE Architecture

sequenceDiagram
    autonumber
    actor Agent as Local AI Agent
    participant MCP as FastMCP (eldo)
    participant SSH as SSH ControlMaster
    participant FIFO as interactive.fifo
    participant Eldo as eldo -inter REPL Engine

    Agent->>MCP: eldo(action="run_interactive", command="...")
    MCP->>SSH: Send interactive SPICE command
    SSH->>FIFO: Pipe command via background tail
    FIFO->>Eldo: Process REPL command stream
    Eldo-->>SSH: Stream log output to interactive_out.txt
    SSH-->>MCP: Parse interactive_out.txt response
    MCP-->>Agent: Return parsed SPICE measurement / status

🚀 Tool Reference & Capabilities Matrix

EDA_MCP exposes 5 specialized tool modules via FastMCP:

🛠️ Installation & Setup

1. Requirements

• Python 3.10 or higher
• OpenSSH client on local system
• Remote Linux server access with Cadence Virtuoso, Siemens Eldo, and Siemens Calibre installed

2. Install Dependencies

pip3 install -r requirements.txt

3. Setup Configuration

Copy and configure JSON config templates inside the config/ directory:

cp config/config_remote_control.json.template config/config_remote_control.json
cp config/config_virtuoso.json.template config/config_virtuoso.json
cp config/config_eldo.json.template config/config_eldo.json
cp config/config_scp.json.template config/config_scp.json

Example configuration (config/config_remote_control.json.template):

{
  "ssh_host": "eda-uni",
  "ssh_config_path": "~/.ssh/config",
  "env_setup_cmd": "source /cadence/cshrc"
}

4. Enable SSH Connection Multiplexing (Sub-10ms Speeds)

Add the following snippet to your local ~/.ssh/config:

Host eda-uni
    HostName eda.university.edu
    User chip_designer
    ControlMaster auto
    ControlPath ~/.ssh/control-%r@%h:%p
    ControlPersist 15m

🔌 AI Client Configuration

Claude Desktop

Add to claude_desktop_config.json:

{
  "mcpServers": {
    "eda-mcp": {
      "command": "python3",
      "args": [
        "/absolute/path/to/EDA_MCP/server.py"
      ]
    }
  }
}

Antigravity IDE / Cursor / Windsurf

Add a Stdio MCP server entry:

• Server Name: EDA_MCP
• Command: python3
• Args: /absolute/path/to/EDA_MCP/server.py

Claude Code CLI

claude mcp add eda-mcp -- python3 /absolute/path/to/EDA_MCP/server.py

📊 SPICE Waveform Visualizer (eldo_plotter.py)

EDA_MCP includes a high-performance PyQtGraph waveform oscilloscope for transient SPICE simulation analysis:

python3 src/clients/eldo_plotter.py --file path/to/simulation.raw

Features:

• Multi-pane subplot rendering for voltage and current signals.
• Dynamic signal value labels following crosshairs in real time.
• Synchronized multi-pane X-axis zooming and panning.
• Automatic parse support for Eldo .raw and .spi3 binary/ASCII formats.

📂 Repository Blueprint

🧪 Testing & Verification

Run the unit test suite:

python3 -m unittest discover tests

or with pytest:

pytest tests/

📜 Contributing & License

• 🤝 Contributing & Agent Guidelines: See CONTRIBUTING.md for full Designer & Coder AI Agent contribution directives.
• 📜 Distributed under the MIT License. See LICENSE for details.