ICRTL: The Open-source Industrial-Level Verilog RTL Benchmark

This repository presents the ICRTL Benchmark, a comprehensive collection of industrial-level Verilog RTL design challenges. Sourced from the prestigious National Taiwan Integrated Circuit Design Contest alongside meticulously handcrafted problems, this repository includes complete specifications and reference implementations.

Each challenge targets specific algorithms and hardware modules utilized in the modern IC industry. We designed this collection to serve as a premier RTL benchmark for evaluating PPA (Power, Performance, and Area) optimization on highly complex problems—a level of difficulty previously unexplored in the application of LLMs to EDA and RTL design.

Building this benchmark from scratch presented significant obstacles, particularly in ensuring seamless compatibility with open-source synthesis tools like Yosys without relying on proprietary IPs. We successfully overcame these barriers to provide a 100% open-source compatible flow, thanks to the incredible efforts of our development team.

Challenges Overview

The repository is organized into problem-specific directories (Q1 through Q6), each containing the problem specification, testbench, and reference solution foundation.

Directory Structure

ICRTL/
├── Q1_LBP/           # Local Binary Pattern Challenge
├── Q2_CONV/          # Convolution Challenge
├── Q3_HC/            # Huffman Coding Challenge
├── Q4_JAM/           # Job Assignment Machine Challenge
├── Q5_DT/            # Distance Transform Challenge
├── Q6_REF/           # Optical Refraction Challenge
├── Q7_GEO/           # Geofence Challenge
├── Q8_IOT/           # IoT Data Filtering Challenge
├── Q9_SECC/          # Set Element Coverage Counter Challenge
├── Q10_GEMM/         # Systolic Array Challenge
├── PROMPT_Generate.  # Referenced Prompts for generating SPEC, Code Generation, and Code Optimization
└── VCS/              # Synopsys VCS / Design Compiler / PrimeTime Evaluation Flow
    ├── eval/         # Main evaluation scripts (auto_cycle.py, run_all.py)
    ├── 01_RTL/       # RTL Simulation setup
        ├── 01_run
        ├── rtl_01.f
    ├── 02_SYN/       # Synthesis setup
        ├── 02_run
        ├── syn.sdc
        ├── syn.tcl    # Remind for the location of PDK or Foundary 
        ├── filelist.v
    ├── 03_GATE/      # Gate-level Simulation setup
        ├── 03_run
        ├── gate_sim.f
    └── 04_POWER/     # Power Analysis setup
        ├── 04_run
        ├── pt_script.tcl  # Remind for the location of PDK or Foundary 

Each Q* folder typically contains:

• 00_TB/: Testbench files and golden data.
• ref_solution/: Reference solutions (can be executed on Yosys - no DesignWare).
• SPEC.md: LLM-readable SPEC extracted from Original_SPEC, including a description of the current implementation.
• Original_SPEC.pdf: The original version of the SPEC written in Chinese.
• 01_run.sh: Shell script for open-source flow execution.

Quick Start: Installing Yosys (OSS CAD Suite)

The yosys package available via some Linux distro package managers (e.g. apt) can be quite old (e.g. 0.9), which lacks full SystemVerilog support (-sv parsing of constructs like .* implicit port connections) and is significantly slower on large designs. We recommend installing the latest nightly build via OSS CAD Suite.

Steps:

1. Download and extract the latest linux-x64 release (release filenames are date-stamped, so grab the actual asset name from the releases page rather than guessing it):

   cd ~
   URL=$(curl -s https://api.github.com/repos/YosysHQ/oss-cad-suite-build/releases/latest \
     | grep "browser_download_url.*linux-x64" | cut -d '"' -f 4)
   wget -O oss-cad-suite.tgz "$URL"
   tar xzf oss-cad-suite.tgz
   

2. Add it to your PATH (prepend so it takes priority over any older system/conda yosys):

   echo 'export PATH="$HOME/oss-cad-suite/bin:$PATH"' >> ~/.bashrc
   source ~/.bashrc
   

3. Verify the install:

   yosys -V
   which yosys   # should point to ~/oss-cad-suite/bin/yosys
   

Note: If you use a conda environment, double-check which yosys afterwards — conda environments can prepend their own bin/ to PATH and shadow the OSS CAD Suite build.

Quick Start: Installing the PDK (NanGate45)

The synthesis scripts (02_run / 01_run.sh) reference a .lib file from the NanGate45 Synopsys-enablement PDK. Clone it to a fixed path at ~/pdk/ so the paths in this repo's scripts work without modification:

mkdir -p ~/pdk
cd ~/pdk
git clone https://github.com/ABKGroup/NanGate45-Synopsys-Enablement.git

This results in the following path, which the scripts expect:

~/pdk/NanGate45-Synopsys-Enablement/NanGate45/lib/NangateOpenCellLibrary_typical.lib

Verify the file exists:

ls -la ~/pdk/NanGate45-Synopsys-Enablement/NanGate45/lib/NangateOpenCellLibrary_typical.lib

No internet access on the target machine? Clone the repo on a machine that has internet access, tar czf it, scp it over, then tar xzf it into ~/pdk/ on the target machine.

Using a different path? If you'd rather keep the PDK somewhere else, update the LIB variable at the top of each problem's synthesis script (e.g. 01_run.sh) accordingly.

How to Run

There are two primary ways to run the designs: using the provided open-source scripts (Icarus Verilog + Yosys) or the commercial tool flow (VCS). Remind the location of your PDK files.

Method 1: Open-Source Flow (Icarus Verilog & Yosys)

Each problem folder contains a 01_run.sh script that runs simulation using iverilog and synthesis using yosys.

Prerequisites:

• iverilog (Icarus Verilog)
• yosys (Yosys Open SYnthesis Suite) — see Quick Start: Installing Yosys above for installing an up-to-date build
• NanGate45 PDK installed at ~/pdk/ — see Quick Start: Installing the PDK above

Steps:

1. Navigate to the problem directory (e.g., Q1_LBP).
2. Execute the run script:

   cd Q1_LBP
   bash 01_run.sh
   

Method 2: VCS / Evaluation Flow

The VCS directory contains a Python-based evaluation framework designed for a more comprehensive analysis (RTL sim, Synthesis, Power).

Prerequisites:

• Synopsys VCS
• Synopsys Design Compiler (DC)
• Synopsys PrimeTime (PT)
• Python 3

Steps:

1. Navigate to VCS/eval.
2. Run the main evaluation script:

   cd VCS/eval
   python3 run_all.py
   

   Note: You may need to edit run_all.py to select which questions to run by modifying the QUESTIONS list.